This invention relates to a voltage boost circuit, and more particularly to a low supply voltage sampling switch circuit using such a voltage boost circuit.
Voltage sampling switch circuits such as used in analog to digital converters (ADC) are desired to conduct even when the input voltage is close to or exceeds the supply voltage. This is becoming more of a challenge as the demand increases for circuits that operate at ever lower supply voltages. Presently, there are no practical 12 bit ADC""s which operate at 1.6 volts although they are in demand. In one approach a transmission gate using a parallel PMOS, NMOS pair works well when the supply voltage is high but the conductance goes to zero about midband of the input when the supply voltage is in the 1.8 volt range. Another approach to the problem, Singer et al., U.S. Pat. No. 6,118,326, employs a boost capacitor which is charged to supply voltage in one mode then stacked on the analog input voltage to provide a fixed enhancement to the gate voltage of the sampling switch to maintain near constant conduction over the input range. One problem with this is that with positive supply voltage using an NMOS switch to connect the boost capacitor to the supply voltage another boost circuit is needed to keep the gate of this NMOS switch above the supply so that the boost capacitor can be sufficiently charged. This uses additional power and requires a clock to constantly recharge this additional boost circuit. In the situation of a positive supply voltage this problem can be alleviated by using a PMOS instead of an NMOS switch but then the back gate of the PMOS normally connected to the source terminal acts as a forward biased diode in the boost mode and quickly discharges the boost capacitor. Other circuits, Pierre Favrat et al., IJSSC March 1998, double the supply voltage to drive the gate. The problem with this is that the boosted voltage can in some conditions of input voltage exceed the maximum voltage rating of the MOS devices and so further adjustment is required to accommodate this. See U.S. Pat. No. 6,118,326 to Singer et al., issued Sep. 12, 2000, entitled Two Phase Boostrap CMOS Switch Drive Technique and Circuit. See also A High Efficiency CMOS Voltage Doubler (Pierre Favrat et al., IJSSC March 1998); a 10-bit 20-MS/s, 35 mw Pipeline A/D Converter (Cho et al., IEEE 1994 custom IC Conf.); and An Experimental 1.5v 64-Mb DRAM (Nakagome et al., IJSSC April 1991).
It is therefore an object of this invention to provide an improved voltage boost circuit.
It is a further object of this invention to provide an improved low supply voltage sampling switch circuit using such a voltage boost circuit.
It is a further object of this invention to provide such an improved voltage boost circuit and low supply voltage sampling switch circuit using such a voltage boost circuit which operate over a wider supply voltage range.
It is a further object of this invention to provide such an improved voltage boost circuit and low supply voltage sampling switch circuit using such a voltage boost circuit which do not require a continuous clock or additional boost circuitry.
It is a further object of this invention to provide such an improved voltage boost circuit and low supply voltage sampling switch circuit using such a voltage boost circuit which stacks the boost capacitor voltage on a fixed bias to ensure that the boosted voltage does not exceed a maximum safe voltage for the MOS devices.
The invention results from the realization that a high voltage boost circuit particularly useful in a low supply voltage sampling switch circuit which uses less power, does not require a continuous clock and operates over a wider range of voltages can be achieved by using a back gate isolation circuit for switching the back gate of a charging MOS switch to reverse bias it both during the charging and the boost modes to prevent charge loss of the capacitor during the boost mode.
This invention features a voltage boost circuit including a boost capacitor and a charging circuit for charging in the charging mode the boost capacitor to a supply voltage. The charging circuit includes a charging MOS switch interconnected between the supply voltage and one terminal of the boost capacitor. There is a boost bias voltage and a boost switch for connecting the second terminal of the boost capacitor to the boost bias voltage in the boost mode. The charging circuit also includes a back gate isolation circuit connected to the back gate of the charging MOS switch and includes a first switch for connecting the back gate to the supply voltage for reverse biasing the back gate in the charging mode and a second switch for connecting the back gate to the one terminal of the boost capacitor for reverse biasing the back gate in the boost mode to prevent charge loss from the boost capacitor.
In a preferred embodiment correct level driving signals are achieved by connecting the last stage of the driving circuit to one terminal of the boost capacitor to provide a driving voltage that is always equal to the largest voltage in the circuit. The supply voltage may be positive and the charging MOS switch may include a PMOS switch. The supply voltage may be negative and the charging MOS switch may include an NMOS switch. The first and second switches each may have their back gates connected to the back gate of the charging MOS switch.
This invention also features a low supply sampling switch circuit with a voltage boost circuit including a boost capacitor and a charging circuit for charging in a charge mode the boost capacitor to a supply voltage. The charging circuit includes a charging MOS switch interconnected between the supply voltage and one terminal of the boost capacitor. There is a boost bias voltage and a boost switch for connecting the second terminal of the boost capacitor to the boost bias voltage in the boost mode. The charging circuit also includes a back gate isolation circuit connected to the back gate of the PMOS switch and includes a first switch for connecting the back gate to the supply voltage for reverse biasing the back gate in the charging mode and a second switch for connecting the back gate to the terminal of the boost capacitor for reverse biasing the back gate in the boost mode to prevent charge loss from the boost capacitor. There is an MOS sampling switch and a boost switch for interconnecting in the boost mode the one terminal of the boost capacitor with the gate of the sampling switch for maintaining the sampling switch in the conducting state.
In a preferred embodiment the supply voltage may be positive, the charging MOS switch may be a PMOS switch and the MOS sampling switch may be an NMOS switch and the sampling switch may conduct even at higher input voltages. The supply voltage may be negative, the charging MOS switch may be an NMOS switch and the MOS sampling switch may be a PMOS switch and the sampling switch may conduct even at lower input voltages. The first and second switches may each have their back gates connected to the back gate of the charging MOS switch.